1. Field of the Invention
The present invention relates to a data processing equipment and a method of the same, more specifically to a data processing equipment and a method of the same suitable for use in, for example, the definition creation technique that generates the HD (High Definition) TV pictorial image from the SD (Standard Definition) TV pictorial image, the adaptive decoding in the compression coding, and the space-time thinning interpolation and suchlike.
2. Description of Related Art
The class classifying technique employing the ADRC (Adaptive Dynamic Range Coding) calculates a class every time at each pixel, while shifting taps forming a class at each pixel. As shown in FIG. 4, in case of, for example, forming a class with 15 taps in the horizontal direction, the class classifying technique fetches a data of 15 pixels forming a tap, detects the maximum value and the minimum value of the data, calculates the dynamic range, and thereafter executes the coding by the ADRC.
FIG. 5 is a block diagram showing a construction of one example of the ADRC class generating circuit. The ADRC class generating circuit is comprised of registers 1-1 through 1-16 and a class code generating circuit 17-1. Next, the class code generating circuit 17-1 will be described.
In accordance with a clock signal, a data corresponding to the pixel value of one pixel inputted from an input terminal not illustrated, which is hereinafter referred to as a pixel data, is supplied to the register 1-1, and a register 2, comparator 4, register 8, and comparator 10 which constitute the class code generating circuit 17-1. And, a load signal LD1 is supplied to AND gates 3, 9 and registers 5, 12.
And, a load signal LD2 and enable signal OE1 are supplied to a register (class generating circuit) 16. The load signal LD2 and enable signal OE1 are designed such that the levels of the signals become low (L) at every 15th clock.
The pixel data supplied to the register 1-1 are supplied to the register 1-2 in accordance with the clock signal. In the same manner, the pixel data supplied to the register 1-2 are sequentially delayed one clock each in accordance with the clock signal, and are transferred to the register 1-16. The pixel data outputted from the register 1-16 are supplied to an adder 6.
On the other hand, a minimum value MIN is detected by the register 2, comparator 4, and AND gate 3, which is supplied to the register 5. The comparator 4 compares a data supplied to a terminal A thereof through the register 2 with a data supplied to a terminal B thereof; and if the data supplied to the terminal A is larger, the output signal level thereof is made low. The low level signal output from the comparator 4 is supplied as a load pulse to the register 2 through the AND gate 3. Thereby, a new data (pixel data supplied to the terminal B) is taken in and held in the register 2. Finally, in this manner, the minimum pixel data of the 15 pixel data is held in the register 2.
At a timing when the LD1 signal level becomes L, the minimum value MIN held in the register 2 is taken in in the register 5. And, the minimum value MIN is held in the register 5 and supplied to the adder 6. The adder 6 adds a pixel data supplied from the register 1-16 and a data that the sign of the minimum value MIN supplied from the register 5 is inverted; and a data (pixel data--minimum value MIN) as the addition result is supplied to a quantization circuit 14 through a register 7.
And, a maximum value MAX is detected by the register 8, comparator 10, and AND gate 9, which is supplied to an adder 11. The comparator 10 compares, in the same manner as in the comparator 4, a data supplied to a terminal A thereof with a data supplied to a terminal B thereof; and if the data supplied to the terminal A is larger, the output signal level thereof is made low. The low level signal output from the comparator 10 is supplied as a load pulse to the register 8 through the AND gate 9. Thereby, a new pixel data (pixel data supplied to the terminal A) is taken in and held in the register 8. In this manner, finally, the maximum pixel data of the 15 pixel data is held in the register 8.
The adder 11 adds the maximum value MAX supplied from the register 8 and a data that the sign of the minimum value MIN supplied from the register 2 is inverted; and thereby, a dynamic range is calculated. The calculated dynamic range DR is supplied to the register 12 and held therein. The dynamic range DR held in the register 12 is supplied to the quantization circuit 14 through a register 13. The quantization circuit 14 quantizes the pixel data to be supplied to the class generating circuit 16, from the pixel data supplied from the register 7 and the dynamic range DR supplied from the register 13.
The pixel data quantized in the quantization circuit 14 are sequentially supplied to a register 15-1 and transferred to a register 15-8 in accordance with the clock signal. The quantized pixel data held in the registers 15-1 through 15-7 are each transferred to the next registers, and the quantized pixel data held in the register 15-8 are supplied to the class generating circuit 16. In the class generating circuit 16, one class code is generated from the eight pixel data quantized to be outputted.
The quantization circuit 14 is composed of, for example, a ROM (Read Only Memory). In this case, the dynamic range DR supplied from the register 13, data (pixel data--minimum MIN) supplied from the register 7, and the quantization code corresponding to these data are associated each other and stored therein.
However, in the foregoing circuit, to calculate a class code accompanies a delay of more than 30 clocks in the throughput. Further, in order to calculate a class code in real time at each time when the pixel under watch is shifted one by one, as shown in FIG. 6, it is necessary to array 15 class generating circuits in parallel, and to select the class codes to be outputted. Accordingly, the hardware becomes considerably bulky, which is a problem. Especially, the part of the quantization is made up of ROMs, which makes the hardware bulky.